Checkpoint — the memory wall

01how

A 4 GHz core stalls on a main-memory fetch that takes 80 ns. Roughly how many instruction slots does that one miss cost?

1. a~30
2. b~80
3. c~320
4. d~4000

02how

A loop reads one 4-byte field from structs laid out at a 64-byte stride. What fraction of the memory bandwidth it consumes is useful?

1. aAll of it — the CPU fetches only what is addressed
2. b1/4
3. c1/16
4. dIt depends on the compiler

03why

Why can't the hardware prefetcher hide the latency of a linked-list traversal, regardless of cache size or clock speed?

1. aLinked lists are stored in a slower region of DRAM
2. bThe next node's address lives inside the current node, so it cannot even be computed until the current load completes — each step is a serialized, unhidable miss
3. cPrefetchers only operate on arrays of primitive types
4. dThe prefetcher is disabled when the branch predictor is busy

04why

Your first micro-benchmark of a summation loop reports a time near zero — hundreds of times faster than the arithmetic allows. What most likely happened?

1. aThe prefetcher preloaded the entire array into L1
2. bThe results were never used, so the optimizer deleted the loop — you timed nothing
3. cThe OS scheduler gave the benchmark a dedicated core
4. dThe array was small enough to fit in registers

05what

What is the unit of transfer between main memory and the cache hierarchy on the platforms Unity targets?

1. a1 byte
2. b16 bytes
3. c64-byte cache line
4. d4 KB page